#include <linux/init.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/gpio.h>
#include <linux/spi/spi.h>
#include <asm/mach/map.h>
#include <mach/pmu.h>
#include <mach/clock.h>
#include <mach/board_config.h>
#include <mach/io.h>


static struct fh_clk osc_clk = {
	.name               = "osc_clk",
	.frequency          = OSC_FREQUENCY,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk ddr_clk = {
	.name               = "ddr_clk",
	.flag               = CLOCK_DDR | CLOCK_NOGATE,
	.div_reg_offset     = VA_CEN_GLB_APB_REG_BASE + 0x438,
	.div_reg_mask       = 0xf000007,
	.div_reg_offset1    = VA_CEN_GLB_APB_REG_BASE + 0x43c,
	.div_reg_mask1      = 0x7ff,
};

static struct fh_clk pll_clk = {
	.name               = "pll_clk",
	.flag               = CLOCK_PLL | CLOCK_NOGATE,
	.div_reg_offset     = VA_CEN_GLB_APB_REG_BASE + 0x41c,
	.div_reg_mask       = 0x7,
	.div_reg_offset1    = VA_CEN_GLB_APB_REG_BASE + 0x420,
	.div_reg_mask1      = 0x7ff,
};

static struct fh_clk pll_div2 = {
	.name               = "pll_div2",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_clk},
	.prediv             = 2,
};

static struct fh_clk pll_div3 = {
	.name               = "pll_div3",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_clk},
	.prediv             = 3,
};

static struct fh_clk pll_div7 = {
	.name               = "pll_div7",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_clk},
	.prediv             = 7,
};

static struct fh_clk pll_div5 = {
	.name               = "pll_div5",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_clk},
	.prediv             = 5,
};

static struct fh_clk pll_div72 = {
	.name               = "pll_div72",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_clk},
	.prediv             = 72,
};

static struct fh_clk pll_900m = {
	.name               = "pll_900m",
	.frequency          = 900000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk pll_600m = {
	.name               = "pll_600m",
	.frequency          = 600000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk pll_514m = {
	.name               = "pll_514m",
	.frequency          = 514000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk pll_360m = {
	.name               = "pll_360m",
	.frequency          = 360000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk pll_257m = {
	.name               = "pll_257m",
	.frequency          = 257000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk rtc = {
	.name               = "rtc",
	.frequency          = 32768,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk rtc_gate = {
	.name               = "rtc_gate",
	.flag               = CLOCK_NODIV,
	.parent             = {&rtc},
	.prediv             = 1,
	.en_reg_offset		= VA_VEU_SYS_AHB_REG_BASE + 0x14,
	.en_reg_mask		= 0x800,
};

/*top*/
static struct fh_clk pll_200m_top = {
	.name               = "pll_200m_top",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_600m},
	.prediv             = 3,
};

static struct fh_clk pll_100m_top = {
	.name               = "pll_100m_top",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_600m},
	.prediv             = 6,
};

static struct fh_clk pll_128_5m_top = {
	.name               = "pll_128_5m_top",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_257m},
	.prediv             = 2,
};

static struct fh_clk pll_75m_top = {
	.name               = "pll_75m_top",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_div3},
	.prediv             = 8,
};

static struct fh_clk pll_64_25m_top = {
	.name               = "pll_64_25m_top",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_div7},
	.prediv             = 4,
};

static struct fh_clk pll_50m_top = {
	.name               = "pll_50m_top",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_div3},
	.prediv             = 12,
};

static struct fh_clk pll_33_3m_top = {
	.name               = "pll_33_3m_top",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_div3},
	.prediv             = 18,
};

static struct fh_clk pll_25m_top = {
	.name               = "pll_25m_top",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_div72},
	.prediv             = 1,
};

static struct fh_clk xtl_24m_top = {
	.name               = "xtl_24m_top",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.prediv             = 1,
};
/*cpu*/
static struct fh_clk pll_600m_cpu = {
	.name               = "pll_600m_cpu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_600m},
	.prediv             = 1,
};

static struct fh_clk pll_450m_cpu = {
	.name               = "pll_450m_cpu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_900m},
	.prediv             = 2,
};

static struct fh_clk pll_225m_cpu2 = {
	.name               = "pll_225m_cpu2",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_450m_cpu},
	.prediv             = 2,
};

static struct fh_clk pll_450_1m_cpu = {
	.name               = "pll_450_1m_cpu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_div2},
	.prediv             = 2,
};

static struct fh_clk pll_300m_cpu = {
	.name               = "pll_300m_cpu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_600m},
	.prediv             = 2,
};

static struct fh_clk pll_150m_cpu2 = {
	.name               = "pll_150m_cpu2",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_300m_cpu},
	.prediv             = 2,
};

static struct fh_clk pll_300_1m_cpu = {
	.name               = "pll_300_1m_cpu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_div3},
	.prediv             = 2,
};

static struct fh_clk pll_257m_cpu = {
	.name               = "pll_257m_cpu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_257m},
	.prediv             = 1,
};

static struct fh_clk pll_128_5m_cpu2 = {
	.name               = "pll_128_5m_cpu2",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_257m_cpu},
	.prediv             = 2,
};

static struct fh_clk pll_257_1m_cpu = {
	.name               = "pll_257_1m_cpu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_div7},
	.prediv             = 1,
};

static struct fh_clk pll_200m_cpu = {
	.name               = "pll_200m_cpu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_600m},
	.prediv             = 3,
};

static struct fh_clk pll_200_1m_cpu = {
	.name               = "pll_200_1m_cpu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_div3},
	.prediv             = 3,
};

static struct fh_clk pll_225m_cpu = {
	.name               = "pll_225m_cpu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_900m},
	.prediv             = 4,
};

static struct fh_clk pll_180_1m_cpu = {
	.name               = "pll_180_1m_cpu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_div5},
	.prediv             = 2,
};

static struct fh_clk pll_150m_cpu = {
	.name               = "pll_150m_cpu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_600m},
	.prediv             = 4,
};

static struct fh_clk pll_128_5m_cpu = {
	.name               = "pll_128_5m_cpu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_257m},
	.prediv             = 2,
};

static struct fh_clk pll_100m_cpu = {
	.name               = "pll_100m_cpu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_div3},
	.prediv             = 6,
};

static struct fh_clk pll_50m_cpu = {
	.name               = "pll_50m_cpu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_div3},
	.prediv             = 12,
};

static struct fh_clk pll_25m_cpu = {
	.name               = "pll_25m_cpu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_div72},
	.prediv             = 1,
};

static struct fh_clk xtl_24m_cpu = {
	.name               = "xtl_24m_cpu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.prediv             = 1,
};

static struct fh_clk pll_20m_cpu = {
	.name               = "pll_20m_cpu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_div5},
	.prediv             = 18,
};

static struct fh_clk xtl_1m_cpu = {
	.name               = "xtl_1m_cpu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.prediv             = 24,
};
/*isp*/
static struct fh_clk pll_360m_isp = {
	.name               = "pll_360m_isp",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_360m},
	.prediv             = 1,
};

static struct fh_clk pll_180m_isp2 = {
	.name               = "pll_180m_isp2",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_360m_isp},
	.prediv             = 2,
};

static struct fh_clk pll_257m_isp = {
	.name               = "pll_257m_isp",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_257m},
	.prediv             = 1,
};

static struct fh_clk pll_128_5m_isp = {
	.name               = "pll_128_5m_isp",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_257m_isp},
	.prediv             = 2,
};

static struct fh_clk pll_200m_isp = {
	.name               = "pll_200m_isp",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_600m},
	.prediv             = 3,
};

static struct fh_clk pll_100m_isp2 = {
	.name               = "pll_100m_isp2",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_200m_isp},
	.prediv             = 2,
};

static struct fh_clk pll_180m_isp = {
	.name               = "pll_180m_isp",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_360m},
	.prediv             = 2,
};

static struct fh_clk pll_100m_isp = {
	.name               = "pll_100m_isp",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_div3},
	.prediv             = 6,
};

static struct fh_clk pll_50m_isp = {
	.name               = "pll_50m_isp",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_div3},
	.prediv             = 12,
};

static struct fh_clk xtl_24m_isp = {
	.name               = "xtl_24m_isp",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.prediv             = 1,
};
/*veu*/
static struct fh_clk xtl_24m_veu = {
	.name               = "xtl_24m_veu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.prediv             = 1,
};

static struct fh_clk pll_600m_veu = {
	.name               = "pll_600m_veu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_600m},
	.prediv             = 1,
};

static struct fh_clk pll_300m_veu = {
	.name               = "pll_300m_veu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_600m_veu},
	.prediv             = 2,
};

static struct fh_clk pll_514m_veu = {
	.name               = "pll_514m_veu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_514m},
	.prediv             = 1,
};

static struct fh_clk pll_450m_veu = {
	.name               = "pll_450m_veu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_900m},
	.prediv             = 2,
};

static struct fh_clk pll_225m_veu = {
	.name               = "pll_225m_veu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_450m_veu},
	.prediv             = 2,
};

static struct fh_clk pll_360m_veu = {
	.name               = "pll_360m_veu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_360m},
	.prediv             = 1,
};

static struct fh_clk pll_180m_veu = {
	.name               = "pll_180m_veu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_360m_veu},
	.prediv             = 2,
};

static struct fh_clk pll_128_5m_veu = {
	.name               = "pll_128_5m_veu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_257m},
	.prediv             = 2,
};

static struct fh_clk pll_64_25m_veu2 = {
	.name               = "pll_64_25m_veu2",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_128_5m_veu},
	.prediv             = 2,
};

static struct fh_clk pll_100m_veu = {
	.name               = "pll_100m_veu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_div3},
	.prediv             = 6,
};

static struct fh_clk pll_64_25m_veu = {
	.name               = "pll_64_25m_veu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_div7},
	.prediv             = 4,
};

static struct fh_clk pll_50m_veu = {
	.name               = "pll_50m_veu",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_div3},
	.prediv             = 12,
};
/*dmc*/
static struct fh_clk xtl_24m_dmc = {
	.name               = "xtl_24m_dmc",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.prediv             = 1,
};

static struct fh_clk pll_50m_dmc = {
	.name               = "pll_50m_dmc",
	.flag               = CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&pll_div3},
	.prediv             = 12,
};

static struct fh_clk ddrpll_dmc = {
	.name               = "ddrpll_dmc",
	.frequency          = 800000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk glb_apb_low = {
	.name               = "glb_apb",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NOGATE,
	.parent             = {&xtl_24m_top, &pll_75m_top,
					&pll_64_25m_top, &pll_100m_top},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x20,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x20,
	.div_reg_mask       = 0x700,
};

static struct fh_clk glb_apb_high = {
	.name               = "glb_apb",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NOGATE,
	.parent             = {&xtl_24m_top, &pll_75m_top,
					&pll_128_5m_top, &pll_200m_top},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x20,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x20,
	.div_reg_mask       = 0x700,
};

static struct fh_clk pts_clk = {
	.name               = "pts_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&xtl_24m_top, &pll_25m_top, &pll_50m_top},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x24,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x24,
	.div_reg_mask       = 0x3f00,
	.en_reg_offset		= VA_CEN_GLB_APB_REG_BASE + 0x400,
	.en_reg_mask		= 0x1,
};

static struct fh_clk sensor0_clk = {
	.name               = "sensor0_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&xtl_24m_top, &pll_33_3m_top,
					&pll_64_25m_top, &pll_75m_top},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x28,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x28,
	.div_reg_mask       = 0xf00,
	.en_reg_offset		= VA_CEN_GLB_APB_REG_BASE + 0x400,
	.en_reg_mask		= 0x2,
};

static struct fh_clk sensor1_clk = {
	.name               = "sensor1_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&xtl_24m_top, &pll_33_3m_top,
					&pll_64_25m_top, &pll_75m_top},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x2c,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x2c,
	.div_reg_mask       = 0xf00,
	.en_reg_offset		= VA_CEN_GLB_APB_REG_BASE + 0x400,
	.en_reg_mask		= 0x4,
};

static struct fh_clk pmu_clk = {
	.name               = "pmu_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&rtc, &xtl_24m_top, &pll_75m_top},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x38,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x38,
	.div_reg_mask       = 0xf00,
	.en_reg_offset		= VA_CEN_GLB_APB_REG_BASE + 0x200,
	.en_reg_mask		= 0x100,
};

static struct fh_clk deb_clk = {
	.name               = "deb_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&rtc, &xtl_24m_top, &pll_33_3m_top,
					&pll_75m_top},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x3c,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x3c,
	.div_reg_mask       = 0xf00,
	.en_reg_offset		= VA_CEN_GLB_APB_REG_BASE + 0x200,
	.en_reg_mask		= 0x200,
};

static struct fh_clk ca7_core_clk_low = {
	.name               = "ca7_core_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&xtl_24m_cpu, &pll_225m_cpu,
					&pll_600m_cpu, &pll_450m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x20,
	.sel_reg_mask       = 0x3,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0x0,
	.en_reg_mask		= 0x1,
};

static struct fh_clk ca7_bus_clk_low = {
	.name               = "ca7_bus_clk",
	.parent             = {&ca7_core_clk_low},
	.prediv             = 1,
	.div_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x24,
	.div_reg_mask       = 0x700,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0x0,
	.en_reg_mask		= 0x20,
};

static struct fh_clk ca7_dbg_clk_low = {
	.name               = "ca7_dbg_clk",
	.flag               = CLOCK_NOGATE,
	.parent             = {&ca7_core_clk_low},
	.prediv             = 1,
	.div_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x28,
	.div_reg_mask       = 0x700,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0x1c0,
	.en_reg_mask		= 0x40000000,
};

static struct fh_clk ca7_core_clk_high = {
	.name               = "ca7_core_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&xtl_24m_cpu, &pll_450m_cpu,
					&pll_600m, &pll_900m},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x20,
	.sel_reg_mask       = 0x3,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0x0,
	.en_reg_mask		= 0x1,
};

static struct fh_clk ca7_bus_clk_high = {
	.name               = "ca7_bus_clk",
	.parent             = {&ca7_core_clk_high},
	.prediv             = 1,
	.div_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x24,
	.div_reg_mask       = 0x700,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0x0,
	.en_reg_mask		= 0x20,
};

static struct fh_clk ca7_dbg_clk_high = {
	.name               = "ca7_dbg_clk",
	.flag               = CLOCK_NOGATE,
	.parent             = {&ca7_core_clk_high},
	.prediv             = 1,
	.div_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x28,
	.div_reg_mask       = 0x700,
};

static struct fh_clk cs_dbg_clk_high = {
	.name               = "cs_dbg_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&xtl_24m_cpu, &pll_100m_cpu, &pll_200m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x2c,
	.sel_reg_mask       = 0x3,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0x1c0,
	.en_reg_mask		= 0x10000000,
};

static struct fh_clk cs_dbg_clk_low = {
	.name               = "cs_dbg_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&xtl_24m_cpu, &pll_100m_cpu, &pll_100m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x2c,
	.sel_reg_mask       = 0x3,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0x1c0,
	.en_reg_mask		= 0x10000000,
};

static struct fh_clk arc_clk_low = {
	.name               = "arc_clk",
	.flag               = CLOCK_NODIV,
	.parent             = {&ca7_core_clk_low},
	.prediv             = 2,
	.en_reg_offset      = VA_CPU_SYS_AHB_REG_BASE + 0x1d0,
	.en_reg_mask        = 0x2,
};

static struct fh_clk arc_clk_high = {
	.name               = "arc_clk",
	.flag               = CLOCK_NODIV,
	.parent             = {&ca7_core_clk_high},
	.prediv             = 2,
	.en_reg_offset      = VA_CPU_SYS_AHB_REG_BASE + 0x1d0,
	.en_reg_mask        = 0x2,
};

static struct fh_clk i2c0_clk = {
	.name               = "i2c0_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&xtl_24m_cpu, &pll_50m_cpu, &pll_100m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x38,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x38,
	.div_reg_mask       = 0x700,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0xac,
	.en_reg_mask		= 0x8,
	.en_reg_offset1		= VA_CPU_SYS_AHB_REG_BASE + 0xb0,
	.en_reg_mask1		= 0x20,
};

static struct fh_clk i2c1_clk = {
	.name               = "i2c1_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&xtl_24m_cpu, &pll_50m_cpu, &pll_100m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x3c,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x3c,
	.div_reg_mask       = 0x700,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0xac,
	.en_reg_mask		= 0x10,
	.en_reg_offset1		= VA_CPU_SYS_AHB_REG_BASE + 0xb0,
	.en_reg_mask1		= 0x40,
};

static struct fh_clk uart0_clk = {
	.name               = "uart0_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&xtl_24m_cpu, &pll_50m_cpu, &pll_100m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x40,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x40,
	.div_reg_mask       = 0x700,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0xac,
	.en_reg_mask		= 0x200,
	.en_reg_offset1		= VA_CPU_SYS_AHB_REG_BASE + 0xb0,
	.en_reg_mask1		= 0x1000,
};

static struct fh_clk uart1_clk = {
	.name               = "uart1_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&xtl_24m_cpu, &pll_50m_cpu, &pll_100m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x44,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x44,
	.div_reg_mask       = 0x700,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0xac,
	.en_reg_mask		= 0x400,
	.en_reg_offset1		= VA_CPU_SYS_AHB_REG_BASE + 0xb0,
	.en_reg_mask1		= 0x2000,
};

static struct fh_clk uart2_clk = {
	.name               = "uart2_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&xtl_24m_cpu, &pll_50m_cpu, &pll_100m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x48,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x48,
	.div_reg_mask       = 0x700,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0xac,
	.en_reg_mask		= 0x800,
	.en_reg_offset1		= VA_CPU_SYS_AHB_REG_BASE + 0xb0,
	.en_reg_mask1		= 0x2,
};

static struct fh_clk gpio_db_clk = {
	.name               = "gpio_db_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&rtc, &pll_20m_cpu, &xtl_24m_cpu, &pll_50m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x4c,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x4c,
	.div_reg_mask       = 0xff00,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0xac,
	.en_reg_mask		= 0x1000,
};

static struct fh_clk spi1_clk = {
	.name               = "spi1_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&xtl_24m_cpu, &pll_50m_cpu, &pll_100m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x50,
	.sel_reg_mask       = 0x3,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0xb0,
	.en_reg_mask		= 0x100,
	.en_reg_offset1		= VA_CPU_SYS_AHB_REG_BASE + 0xac,
	.en_reg_mask1		= 0x40,
};

static struct fh_clk pwm_clk = {
	.name               = "pwm_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&xtl_24m_cpu, &pll_50m_cpu, &pll_100m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x54,
	.sel_reg_mask       = 0x3,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0xac,
	.en_reg_mask		= 0x20,
	.en_reg_offset1		= VA_CPU_SYS_AHB_REG_BASE + 0xb0,
	.en_reg_mask1		= 0x80,
};

static struct fh_clk stm0_clk = {
	.name               = "stm0_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&xtl_24m_cpu, &pll_50m_cpu, &pll_100m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x58,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x58,
	.div_reg_mask       = 0x700,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0xb0,
	.en_reg_mask		= 0x10000,
	.en_reg_offset1		= VA_CPU_SYS_AHB_REG_BASE + 0xdc,
	.en_reg_mask1		= 0x10000,
};

static struct fh_clk stm1_clk = {
	.name               = "stm1_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&xtl_24m_cpu, &pll_50m_cpu, &pll_100m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x5c,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x5c,
	.div_reg_mask       = 0x700,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0xb0,
	.en_reg_mask		= 0x80000,
	.en_reg_offset1		= VA_CPU_SYS_AHB_REG_BASE + 0xdc,
	.en_reg_mask1		= 0x20000,
};

static struct fh_clk tmr0_clk = {
	.name               = "tmr0_clk",
	.flag               = CLOCK_NODIV,
	.parent             = {&xtl_24m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x60,
	.sel_reg_mask       = 0x1,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0x0,
	.en_reg_mask		= 0x10,
};

static struct fh_clk rtc_tmr0_clk = {
	.name               = "rtc_tmr0_clk",
	.flag               = CLOCK_NODIV,
	.parent             = {&rtc},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x64,
	.sel_reg_mask       = 0x1,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0x0,
	.en_reg_mask		= 0x8,
};

static struct fh_clk syst_clk = {
	.name               = "syst_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&rtc, &xtl_1m_cpu, &xtl_24m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x68,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x68,
	.div_reg_mask       = 0xff00,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0xb0,
	.en_reg_mask		= 0x400,
};

static struct fh_clk spi0_clk = {
	.name               = "spi0_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&xtl_24m_cpu, &pll_180_1m_cpu,
					&pll_200_1m_cpu, &pll_257_1m_cpu,
					&pll_300_1m_cpu, &pll_450_1m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x6c,
	.sel_reg_mask       = 0x7,
	.div_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x6c,
	.div_reg_mask       = 0xff00,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0xb0,
	.en_reg_mask		= 0x8000,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0xb0,
	.en_reg_mask		= 0x4000,
};

static struct fh_clk i2s0_slow_clk = {
	.name               = "i2s0_slow_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&xtl_24m_cpu, &pll_100m_cpu, &pll_128_5m_cpu,
				&pll_150m_cpu, &pll_200m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_AHB_REG_BASE + 0xc4,
	.sel_reg_mask       = 0x1c,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0xb0,
	.en_reg_mask		= 0x4000000,
};

static struct fh_clk i2s0_fast_clk = {
	.name               = "i2s0_fast_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&xtl_24m_cpu, &pll_200m_cpu, &pll_450m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_AHB_REG_BASE + 0xc4,
	.sel_reg_mask       = 0x3,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0xb8,
	.en_reg_mask		= 0x8,
};

static struct fh_clk ts_24m_clk = {
	.name               = "ts_24m_clk",
	.parent             = {&xtl_24m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x70,
	.sel_reg_mask       = 0x1,
	.div_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x70,
	.div_reg_mask       = 0xf00,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0xb0,
	.en_reg_mask		= 0x800000,
};

static struct fh_clk ephy_200m_clk = {
	.name               = "ephy_200m_clk",
	.flag               = CLOCK_NOGATE | CLOCK_NODIV,
	.parent             = {&pll_200m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x78,
	.sel_reg_mask       = 0x1,
};

static struct fh_clk ephy_125m_clk_high = {
	.name               = "ephy_125m_clk",
	.flag               = CLOCK_NOGATE | CLOCK_NODIV,
	.parent             = {&pll_128_5m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x7c,
	.sel_reg_mask       = 0x1,
};

static struct fh_clk ephy_125m_clk_low = {
	.name               = "ephy_125m_clk",
	.flag               = CLOCK_NOGATE | CLOCK_NODIV,
	.parent             = {&pll_128_5m_cpu},
	.prediv             = 2,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x7c,
	.sel_reg_mask       = 0x1,
};

static struct fh_clk ephy_100m_clk = {
	.name               = "ephy_100m_clk",
	.flag               = CLOCK_NOGATE | CLOCK_NODIV,
	.parent             = {&pll_100m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x80,
	.sel_reg_mask       = 0x1,
};

static struct fh_clk ephy0_ref_clk = {
	.name               = "ephy0_ref_clk",
	.parent             = {&pll_25m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x84,
	.sel_reg_mask       = 0x1,
	.div_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x84,
	.div_reg_mask       = 0x300,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0x1fc,
	.en_reg_mask		= 0x4,
};

static struct fh_clk vou_mif_clk_high = {
	.name               = "vou_mif_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&xtl_24m_cpu, &pll_450m_cpu, &pll_600m_cpu,
				&pll_900m},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x88,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x88,
	.div_reg_mask       = 0xff00,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0x1fc,
	.en_reg_mask		= 0x2,
};

static struct fh_clk vou_mif_clk_low = {
	.name               = "vou_mif_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&xtl_24m_cpu, &pll_225m_cpu, &pll_300m_cpu,
				&pll_450m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x88,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x88,
	.div_reg_mask       = 0xff00,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0x1fc,
	.en_reg_mask		= 0x2,
};

static struct fh_clk efuse_clock = {
	.name               = "efuse_clock",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&xtl_24m_cpu, &pll_50m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_CLK_RF_REG_BASE + 0x8c,
	.sel_reg_mask       = 0x1,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0xe0,
	.en_reg_mask		= 0x1,
};

static struct fh_clk dmic0_sr_clock_low = {
	.name               = "dmic0_sr_clock",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&xtl_24m_cpu, &pll_128_5m_cpu2, &pll_150m_cpu2,
				&pll_225m_cpu2},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_AHB_REG_BASE + 0x664,
	.sel_reg_mask       = 0xc00000,
};

static struct fh_clk dmic0_sr_clock_high = {
	.name               = "dmic0_sr_clock",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&xtl_24m_cpu, &pll_257m_cpu, &pll_300m_cpu,
				&pll_450m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_AHB_REG_BASE + 0x664,
	.sel_reg_mask       = 0xc00000,
};

static struct fh_clk dmc_2x_clk = {
	.name               = "dmc_2x_clk",
	.flag               = CLOCK_NODIV,
	.parent             = {&ddrpll_dmc},
	.prediv             = 1,
	.en_reg_offset		= VA_DMC_SYS_APB_REG_BASE + 0x300,
	.en_reg_mask		= 0x1000,
};

static struct fh_clk dmc_1x_clk = {
	.name               = "dmc_1x_clk",
	.parent             = {&dmc_2x_clk},
	.prediv             = 1,
	.div_reg_offset     = VA_DMC_SYS_APB_REG_BASE + 0x300,
	.div_reg_mask       = 0xc00,
	.en_reg_offset		= VA_DMC_SYS_APB_REG_BASE + 0x300,
	.en_reg_mask		= 0x10000000,
};

static struct fh_clk busm_timer_clk = {
	.name               = "busm_timer_clk",
	.flag               = CLOCK_NODIV,
	.parent             = {&xtl_24m_dmc},
	.prediv             = 1,
	.en_reg_offset		= VA_DMC_SYS_APB_REG_BASE + 0x300,
	.en_reg_mask		= 0x100000,
};

static struct fh_clk isp_bus_clk_low = {
	.name               = "isp_bus_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&xtl_24m_isp, &pll_100m_isp2,
				&pll_128_5m_isp},
	.prediv             = 1,
	.sel_reg_offset     = VA_ISP_SYS_APB_REG_BASE + 0x0,
	.sel_reg_mask       = 0x3000000,
	.div_reg_offset     = VA_ISP_SYS_APB_REG_BASE + 0x0,
	.div_reg_mask       = 0xf00000,
	.en_reg_offset		= VA_ISP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask		= 0x4000000,
};

static struct fh_clk isp_bus_clk_high = {
	.name               = "isp_bus_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&xtl_24m_isp, &pll_200m_isp,
				&pll_257m_isp},
	.prediv             = 1,
	.sel_reg_offset     = VA_ISP_SYS_APB_REG_BASE + 0x0,
	.sel_reg_mask       = 0x3000000,
	.div_reg_offset     = VA_ISP_SYS_APB_REG_BASE + 0x0,
	.div_reg_mask       = 0xf00000,
	.en_reg_offset		= VA_ISP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask		= 0x4000000,
};

static struct fh_clk sd0_clk = {
	.name               = "sd0_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&xtl_24m_isp, &pll_50m_isp},
	.prediv             = 1,
	.sel_reg_offset     = VA_ISP_SYS_APB_REG_BASE + 0x4,
	.sel_reg_mask       = 0x10,
	.en_reg_offset		= VA_ISP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask		= 0x2000000,
};

static struct fh_clk ahb_sdio0_gate = {
	.name               = "ahb_sdio0_gate",
	.flag               = CLOCK_NODIV,
	.en_reg_offset		= VA_ISP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask		= 0x40000,
};

static struct fh_clk sd0_dllref_clk = {
	.name               = "sd0_dllref_clk",
	.flag               = CLOCK_NODIV,
	.parent             = {&pll_100m_isp},
	.prediv             = 1,
	.en_reg_offset		= VA_ISP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask		= 0x1000000,
};

static struct fh_clk sd1_clk = {
	.name               = "sd1_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&xtl_24m_isp, &pll_50m_isp},
	.prediv             = 1,
	.sel_reg_offset     = VA_ISP_SYS_APB_REG_BASE + 0x4,
	.sel_reg_mask       = 0x8,
	.en_reg_offset		= VA_ISP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask		= 0x200,
};

static struct fh_clk ahb_sdio1_gate = {
	.name               = "ahb_sdio1_gate",
	.flag               = CLOCK_NODIV,
	.en_reg_offset		= VA_ISP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask		= 0x20000,
};

static struct fh_clk sd1_dllref_clk = {
	.name               = "sd1_dllref_clk",
	.flag               = CLOCK_NODIV,
	.parent             = {&pll_100m_isp},
	.prediv             = 1,
	.en_reg_offset		= VA_ISP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask		= 0x100,
};

static struct fh_clk csi_clk_low = {
	.name               = "csi_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&xtl_24m_isp, &pll_50m_isp, &pll_100m_isp2,
				&pll_100m_isp2},
	.prediv             = 1,
	.sel_reg_offset     = VA_ISP_SYS_APB_REG_BASE + 0x0,
	.sel_reg_mask       = 0x60000000,
	.en_reg_offset		= VA_ISP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask		= 0x10000000,
};

static struct fh_clk csi_clk_high = {
	.name               = "csi_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&xtl_24m_isp, &pll_50m_isp, &pll_100m_isp,
				&pll_200m_isp},
	.prediv             = 1,
	.sel_reg_offset     = VA_ISP_SYS_APB_REG_BASE + 0x0,
	.sel_reg_mask       = 0x60000000,
	.en_reg_offset		= VA_ISP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask		= 0x10000000,
};

static struct fh_clk vicap_clk_low = {
	.name               = "vicap_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&xtl_24m_isp, &pll_128_5m_isp, &pll_180m_isp2},
	.prediv             = 1,
	.sel_reg_offset     = VA_ISP_SYS_APB_REG_BASE + 0x4,
	.sel_reg_mask       = 0xc0,
	.div_reg_offset     = VA_ISP_SYS_APB_REG_BASE + 0x0,
	.div_reg_mask       = 0x1e000,
	.en_reg_offset		= VA_ISP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask		= 0x40,
};

static struct fh_clk vicap_clk_high = {
	.name               = "vicap_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&xtl_24m_isp, &pll_257m, &pll_360m},
	.prediv             = 1,
	.sel_reg_offset     = VA_ISP_SYS_APB_REG_BASE + 0x4,
	.sel_reg_mask       = 0xc0,
	.div_reg_offset     = VA_ISP_SYS_APB_REG_BASE + 0x0,
	.div_reg_mask       = 0x1e000,
	.en_reg_offset		= VA_ISP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask		= 0x40,
};

static struct fh_clk veu_bus_clk_low = {
	.name               = "veu_bus_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&xtl_24m_isp, &pll_64_25m_veu2, &pll_225m_veu,
				&pll_180m_veu},
	.prediv             = 1,
	.sel_reg_offset     = VA_VEU_SYS_AHB_REG_BASE + 0x10,
	.sel_reg_mask       = 0x30,
	.en_reg_offset		= VA_VEU_SYS_AHB_REG_BASE + 0x10,
	.en_reg_mask		= 0x1,
};

static struct fh_clk veu_clk_low = {
	.name               = "veu_clk",
	.parent             = {&veu_bus_clk_low},
	.prediv             = 1,
	.div_reg_offset     = VA_VEU_SYS_AHB_REG_BASE + 0x10,
	.div_reg_mask       = 0xe,
	.en_reg_offset		= VA_VEU_SYS_AHB_REG_BASE + 0x10,
	.en_reg_mask		= 0x80,
};

static struct fh_clk usb2_ahb_clk_low = {
	.name               = "usb2_ahb_clk",
	.parent             = {&veu_bus_clk_low},
	.prediv             = 1,
	.div_reg_offset     = VA_VEU_SYS_AHB_REG_BASE + 0x14,
	.div_reg_mask       = 0x1c000,
	.en_reg_offset		= VA_VEU_SYS_AHB_REG_BASE + 0x10,
	.en_reg_mask		= 0x80000,
};

static struct fh_clk veu_bus_clk_high = {
	.name               = "veu_bus_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&xtl_24m_isp, &pll_128_5m_veu, &pll_360m_veu,
				&pll_360m_veu},
	.prediv             = 1,
	.sel_reg_offset     = VA_VEU_SYS_AHB_REG_BASE + 0x10,
	.sel_reg_mask       = 0x30,
	.en_reg_offset		= VA_VEU_SYS_AHB_REG_BASE + 0x10,
	.en_reg_mask		= 0x1,
};

static struct fh_clk veu_clk_high = {
	.name               = "veu_clk",
	.parent             = {&veu_bus_clk_high},
	.prediv             = 1,
	.div_reg_offset     = VA_VEU_SYS_AHB_REG_BASE + 0x10,
	.div_reg_mask       = 0xe,
	.en_reg_offset		= VA_VEU_SYS_AHB_REG_BASE + 0x10,
	.en_reg_mask		= 0x80,
};

static struct fh_clk usb2_ahb_clk_high = {
	.name               = "usb2_ahb_clk",
	.parent             = {&veu_bus_clk_high},
	.prediv             = 1,
	.div_reg_offset     = VA_VEU_SYS_AHB_REG_BASE + 0x14,
	.div_reg_mask       = 0x1c000,
	.en_reg_offset		= VA_VEU_SYS_AHB_REG_BASE + 0x10,
	.en_reg_mask		= 0x80000,
};

static struct fh_clk nn_clk_low = {
	.name               = "nn_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&xtl_24m_veu, &pll_180m_isp, &pll_257m,
				&pll_300m_veu},
	.prediv             = 1,
	.sel_reg_offset     = VA_VEU_SYS_AHB_REG_BASE + 0x10,
	.sel_reg_mask       = 0x300,
	.en_reg_offset		= VA_VEU_SYS_AHB_REG_BASE + 0x10,
	.en_reg_mask		= 0x400,
};

static struct fh_clk nn_clk_high = {
	.name               = "nn_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&xtl_24m_veu, &pll_360m, &pll_514m_veu,
				&pll_514m_veu},
	.prediv             = 1,
	.sel_reg_offset     = VA_VEU_SYS_AHB_REG_BASE + 0x10,
	.sel_reg_mask       = 0x300,
	.en_reg_offset		= VA_VEU_SYS_AHB_REG_BASE + 0x10,
	.en_reg_mask		= 0x400,
};

static struct fh_clk grp0_500m_clk = {
	.name               = "grp0_500m_clk",
	.flag               = CLOCK_NODIV,
	.parent             = {&pll_450m_veu},
	.prediv             = 1,
	.en_reg_offset		= VA_VEU_SYS_AHB_REG_BASE + 0x10,
	.en_reg_mask		= 0x200000,
};

static struct fh_clk grp1_500m_clk = {
	.name               = "grp1_500m_clk",
	.flag               = CLOCK_NODIV,
	.parent             = {&pll_450m_veu},
	.prediv             = 1,
	.en_reg_offset		= VA_VEU_SYS_AHB_REG_BASE + 0x10,
	.en_reg_mask		= 0x400000,
};

static struct fh_clk grp2_500m_clk = {
	.name               = "grp2_500m_clk",
	.flag               = CLOCK_NODIV,
	.parent             = {&pll_450m_veu},
	.prediv             = 1,
	.en_reg_offset		= VA_VEU_SYS_AHB_REG_BASE + 0x10,
	.en_reg_mask		= 0x800000,
};

static struct fh_clk grp0_62_5m_clk = {
	.name               = "grp0_62_5m_clk",
	.flag               = CLOCK_NODIV,
	.parent             = {&pll_64_25m_veu},
	.prediv             = 1,
	.en_reg_offset		= VA_VEU_SYS_AHB_REG_BASE + 0x10,
	.en_reg_mask		= 0x1000000,
};

static struct fh_clk grp1_62_5m_clk = {
	.name               = "grp1_62_5m_clk",
	.flag               = CLOCK_NODIV,
	.parent             = {&pll_64_25m_veu},
	.prediv             = 1,
	.en_reg_offset		= VA_VEU_SYS_AHB_REG_BASE + 0x10,
	.en_reg_mask		= 0x2000000,
};

static struct fh_clk grp2_62_5m_clk = {
	.name               = "grp2_62_5m_clk",
	.flag               = CLOCK_NODIV,
	.parent             = {&pll_64_25m_veu},
	.prediv             = 1,
	.en_reg_offset		= VA_VEU_SYS_AHB_REG_BASE + 0x10,
	.en_reg_mask		= 0x4000000,
};

static struct fh_clk grp3_62_5m_clk = {
	.name               = "grp3_62_5m_clk",
	.flag               = CLOCK_NODIV,
	.parent             = {&pll_64_25m_veu},
	.prediv             = 1,
	.en_reg_offset		= VA_VEU_SYS_AHB_REG_BASE + 0x10,
	.en_reg_mask		= 0x8000000,
};

static struct fh_clk rtc_24m_clk = {
	.name               = "rtc_24m_clk",
	.flag               = CLOCK_NODIV,
	.parent             = {&xtl_24m_veu},
	.prediv             = 1,
	.en_reg_offset		= VA_VEU_SYS_AHB_REG_BASE + 0x14,
	.en_reg_mask		= 0x200,
};

static struct fh_clk sadc_clk = {
	.name               = "sadc_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&xtl_24m_isp, &pll_64_25m_veu, &pll_100m_veu},
	.prediv             = 1,
	.sel_reg_offset     = VA_VEU_SYS_AHB_REG_BASE + 0x14,
	.sel_reg_mask       = 0x180,
	.div_reg_offset     = VA_VEU_SYS_AHB_REG_BASE + 0x14,
	.div_reg_mask       = 0x7e,
	.en_reg_offset		= VA_VEU_SYS_AHB_REG_BASE + 0x14,
	.en_reg_mask		= 0x1,
	.en_reg_offset1		= VA_VEU_SYS_AHB_REG_BASE + 0x14,
	.en_reg_mask1		= 0x1000,
};

static struct fh_clk acw_clk_gate = {
	.name               = "acw_clk_gate",
	.flag               = CLOCK_NODIV,
	.en_reg_offset		= VA_VEU_SYS_AHB_REG_BASE + 0x14,
	.en_reg_mask		= 0x400,
};

static struct fh_clk dmic_apb_gate = {
	.name               = "dmic_apb_gate",
	.flag               = CLOCK_NODIV,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0xdc,
	.en_reg_mask		= 0x80000,
};

static struct fh_clk wdt_clk = {
	.name               = "wdt_clk",
	.flag               = CLOCK_NODIV,
	.parent             = {&rtc},
	.prediv             = 1,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0xb0,
	.en_reg_mask		= 0x200,
	.en_reg_offset1		= VA_CPU_SYS_AHB_REG_BASE + 0xb0,
	.en_reg_mask1		= 0x10,
};

static struct fh_clk i2s_apb_clk = {
	.name               = "i2s_apb_clk",
	.flag               = CLOCK_NODIV,
	.en_reg_offset		= VA_CPU_SYS_AHB_REG_BASE + 0xb0,
	.en_reg_mask		= 0x400000,
};

struct fh_clk *fh_clks_low[] = {
	&osc_clk,
	&ddr_clk,
	&pll_clk,
	&pll_div2,
	&pll_div3,
	&pll_div7,
	&pll_div5,
	&pll_div72,
	&pll_900m,
	&pll_600m,
	&pll_514m,
	&pll_360m,
	&pll_257m,
	&rtc,
	&rtc_gate,
	&pll_200m_top,
	&pll_100m_top,
	&pll_128_5m_top,
	&pll_75m_top,
	&pll_64_25m_top,
	&pll_50m_top,
	&pll_33_3m_top,
	&pll_25m_top,
	&xtl_24m_top,
	&pll_600m_cpu,
	&pll_450_1m_cpu,
	&pll_450m_cpu,
	&pll_225m_cpu2,
	&pll_300_1m_cpu,
	&pll_257m_cpu,
	&pll_128_5m_cpu2,
	&pll_300m_cpu,
	&pll_150m_cpu2,
	&pll_257_1m_cpu,
	&pll_200_1m_cpu,
	&pll_200m_cpu,
	&pll_225m_cpu,
	&pll_180_1m_cpu,
	&pll_150m_cpu,
	&pll_128_5m_cpu,
	&pll_100m_cpu,
	&pll_50m_cpu,
	&pll_25m_cpu,
	&xtl_24m_cpu,
	&pll_20m_cpu,
	&xtl_1m_cpu,
	&pll_360m_isp,
	&pll_180m_isp2,
	&pll_257m_isp,
	&pll_128_5m_isp,
	&pll_200m_isp,
	&pll_100m_isp2,
	&pll_180m_isp,
	&pll_100m_isp,
	&pll_50m_isp,
	&xtl_24m_isp,
	&pll_600m_veu,
	&pll_300m_veu,
	&pll_514m_veu,
	&pll_450m_veu,
	&pll_225m_veu,
	&pll_360m_veu,
	&pll_180m_veu,
	&pll_128_5m_veu,
	&pll_64_25m_veu2,
	&pll_100m_veu,
	&pll_64_25m_veu,
	&pll_50m_veu,
	&xtl_24m_veu,
	&pll_50m_dmc,
	&xtl_24m_dmc,
	&ddrpll_dmc,
	&glb_apb_low,
	&pts_clk,
	&sensor0_clk,
	&sensor1_clk,
	&pmu_clk,
	&arc_clk_low,
	&deb_clk,
	&ca7_core_clk_low,
	&ca7_bus_clk_low,
	&ca7_dbg_clk_low,
	&cs_dbg_clk_low,
	&i2c0_clk,
	&i2c1_clk,
	&uart0_clk,
	&uart1_clk,
	&uart2_clk,
	&gpio_db_clk,
	&spi1_clk,
	&pwm_clk,
	&stm0_clk,
	&stm1_clk,
	&tmr0_clk,
	&rtc_tmr0_clk,
	&syst_clk,
	&spi0_clk,
	&i2s0_slow_clk,
	&i2s0_fast_clk,
	&ts_24m_clk,
	&ephy_200m_clk,
	&ephy_125m_clk_low,
	&ephy_100m_clk,
	&ephy0_ref_clk,
	&vou_mif_clk_low,
	&efuse_clock,
	&dmic0_sr_clock_low,
	&dmc_2x_clk,
	&dmc_1x_clk,
	&busm_timer_clk,
	&isp_bus_clk_low,
	&sd0_clk,
	&ahb_sdio0_gate,
	&sd0_dllref_clk,
	&sd1_clk,
	&ahb_sdio1_gate,
	&sd1_dllref_clk,
	&csi_clk_low,
	&vicap_clk_low,
	&veu_bus_clk_low,
	&veu_clk_low,
	&usb2_ahb_clk_low,
	&nn_clk_low,
	&grp0_500m_clk,
	&grp1_500m_clk,
	&grp2_500m_clk,
	&grp0_62_5m_clk,
	&grp1_62_5m_clk,
	&grp2_62_5m_clk,
	&grp3_62_5m_clk,
	&rtc_24m_clk,
	&sadc_clk,
	&acw_clk_gate,
	&dmic_apb_gate,
	&wdt_clk,
	&i2s_apb_clk,
	NULL,
};
EXPORT_SYMBOL(fh_clks_low);

struct fh_clk *fh_clks_high[] = {
	&osc_clk,
	&ddr_clk,
	&pll_clk,
	&pll_div2,
	&pll_div3,
	&pll_div7,
	&pll_div5,
	&pll_div72,
	&pll_900m,
	&pll_600m,
	&pll_514m,
	&pll_360m,
	&pll_257m,
	&rtc,
	&rtc_gate,
	&pll_200m_top,
	&pll_100m_top,
	&pll_128_5m_top,
	&pll_75m_top,
	&pll_64_25m_top,
	&pll_50m_top,
	&pll_33_3m_top,
	&pll_25m_top,
	&xtl_24m_top,
	&pll_600m_cpu,
	&pll_450_1m_cpu,
	&pll_450m_cpu,
	&pll_225m_cpu2,
	&pll_300_1m_cpu,
	&pll_257m_cpu,
	&pll_128_5m_cpu2,
	&pll_300m_cpu,
	&pll_150m_cpu2,
	&pll_257_1m_cpu,
	&pll_200_1m_cpu,
	&pll_200m_cpu,
	&pll_225m_cpu,
	&pll_180_1m_cpu,
	&pll_150m_cpu,
	&pll_128_5m_cpu,
	&pll_100m_cpu,
	&pll_50m_cpu,
	&pll_25m_cpu,
	&xtl_24m_cpu,
	&pll_20m_cpu,
	&xtl_1m_cpu,
	&pll_360m_isp,
	&pll_180m_isp2,
	&pll_257m_isp,
	&pll_128_5m_isp,
	&pll_200m_isp,
	&pll_100m_isp2,
	&pll_180m_isp,
	&pll_100m_isp,
	&pll_50m_isp,
	&xtl_24m_isp,
	&pll_600m_veu,
	&pll_300m_veu,
	&pll_514m_veu,
	&pll_450m_veu,
	&pll_225m_veu,
	&pll_360m_veu,
	&pll_180m_veu,
	&pll_128_5m_veu,
	&pll_64_25m_veu2,
	&pll_100m_veu,
	&pll_64_25m_veu,
	&pll_50m_veu,
	&xtl_24m_veu,
	&pll_50m_dmc,
	&xtl_24m_dmc,
	&ddrpll_dmc,
	&glb_apb_high,
	&pts_clk,
	&sensor0_clk,
	&sensor1_clk,
	&pmu_clk,
	&arc_clk_high,
	&deb_clk,
	&ca7_core_clk_high,
	&ca7_bus_clk_high,
	&ca7_dbg_clk_high,
	&cs_dbg_clk_high,
	&i2c0_clk,
	&i2c1_clk,
	&uart0_clk,
	&uart1_clk,
	&uart2_clk,
	&gpio_db_clk,
	&spi1_clk,
	&pwm_clk,
	&stm0_clk,
	&stm1_clk,
	&tmr0_clk,
	&rtc_tmr0_clk,
	&syst_clk,
	&spi0_clk,
	&i2s0_slow_clk,
	&i2s0_fast_clk,
	&ts_24m_clk,
	&ephy_200m_clk,
	&ephy_125m_clk_high,
	&ephy_100m_clk,
	&ephy0_ref_clk,
	&vou_mif_clk_high,
	&efuse_clock,
	&dmic0_sr_clock_high,
	&dmc_2x_clk,
	&dmc_1x_clk,
	&busm_timer_clk,
	&isp_bus_clk_high,
	&sd0_clk,
	&ahb_sdio0_gate,
	&sd0_dllref_clk,
	&sd1_clk,
	&ahb_sdio1_gate,
	&sd1_dllref_clk,
	&csi_clk_high,
	&vicap_clk_high,
	&veu_bus_clk_high,
	&veu_clk_high,
	&usb2_ahb_clk_high,
	&nn_clk_high,
	&grp0_500m_clk,
	&grp1_500m_clk,
	&grp2_500m_clk,
	&grp0_62_5m_clk,
	&grp1_62_5m_clk,
	&grp2_62_5m_clk,
	&grp3_62_5m_clk,
	&rtc_24m_clk,
	&sadc_clk,
	&acw_clk_gate,
	&dmic_apb_gate,
	&wdt_clk,
	&i2s_apb_clk,
	NULL,
};
EXPORT_SYMBOL(fh_clks_high);
